Circuit Topological Speed Optimization of SC-Filters, 1991

I decided to rescue this page from my old web pages and move it to my new pages here. I was working with this project more than 30 years ago!

Jukka Wallinheimo: Circuit Topological Speed Optimization of SC-Filters, 1991

I designed two chips in my master’s thesis and this is a photo of the first one taken with a microscope. The actual size of this piece of silicon is 7.5mm x 3.5mm. It was fabricated with 2.5um CMOS-process MAS7 by Micronas. There is an anti-aliasing filter, a sc-filter, a smoothing filter and a programmable gain amplifier on this system. It has two identical channels and it can be used in an I/Q demodulator in a digital radio receiver modem.

Abstract of The Master’s Thesis:

The purpose of this work has been to find improved structures and synthesis methods for board-band SC-filters. The basic ideas and the traditional approximate filter synthesis of switched capacitor circuits are first presented. Next, the factors slowing down the speed of the filters are discussed. Errors due to approximate synthesis method are also analyzed. Fully differential structures, exact synthesis and flow graph manipulations have been found to be efficient circuit topological means to speed up SC-filters. Two test chips have been designed and realized during this work. Because of process delays measured results are given for one design only.

IC Layout

These are the basic components you can fabricate with a CMOS process. The design above is made out of hundreds of these basic components dimensioned variously. Here are the symbols and how the masks of those components look like drawn in a layout CAD tool.


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